Place and Route Engineer


Place and Route Engineer


  • At least 3-5 years professional experience in microelectronics physical implementation.
  • Good verbal and writing communication skills.
  • Fabrication process variation impacts and performance.
  • Experience in low-power design techniques.
  • Good understanding of ERC, EMI rules and impact on final chip verification and cycle time reduction.
  • Ability to work in a team environment and participate in cross-functional activities.
  • Experience with the following tools:
    • Mandatory: Cadence RTL Compiler, SOC-Encounter/ EDIS, ETS , EPS.
    • Desirable: Mentor Calibre/ Assura.

Job Description /Other Requirements:

  • Power planning, optimization, power grid and signal routing considering timing constraints.
  • Design floor planning, analogue and memory macro placement.
  • Place and route including timing closure.
  • Extraction of layout parasitics and SPEF/ SDF generation. Signal integrity tests.
  • Post-synthesis static timing analysis (STA) and post-layout STA.
  • Physical verification (DRC, ERC, LVS, ANTENNA rules).
  • Writing, running, optimization of scripts for above tasks.
  • Implement and monitor Quality Assurance/ Quality Control standards based on corporate guidelines in a project setting.
  • Have done multiple tapeouts and proven record of designing complex ICs in state of the art CMOS process technologies and has successfully placed products into volume production, preferably multiple times.